Review of GaAs and GaN Microwave and Millimeter - Wave Multifunctional Integrated Circuit Chips

Microwave monolithic integrated circuitshic integrated circuit, MMIC) with its volumeThe advantages of small size, light weight, good consistency and high reliability have been rapidly developed in the microwave and millimeter wave fields.However, as T/R component systems require smaller and smaller volumes, and as assembly efficiency and higher reliability requirements become increasingly stringent, a chip needs to have more functions.An integrated circuit that generally consists of two or more functional circuits integrated on the same substrate (such as GaAs, SiC or Si, etc.) is defined as a multifunctional integrated circuit.The multifunctional chip has higher integration, smaller area and lower cost. The connection between different functional circuits is completed internally, and the number of solder joints is greatly reduced, thus significantly improving the assembly efficiency of T/R components.The most commonly used microwave and millimeter wave compound semiconductor materials include GaAs, GaN, SiGe and InP.Due to the large number of multifunctional types, this article mainly involves GaAs and GaN multifunctional integrated circuit chips, and mainly outlines the receive/transmit multifunctional chips, amplitude and phase multifunctional chips and PIN limiting low noise amplifier chips.The multifunctional receiving/transmitting chip mainly includes a low noise amplifier for the receiving branch, a power amplifier for the transmitting branch, and an input/output conversion switch.The multi-function of transmitting/receiving can be realized by power amplifier technology, low noise technology or ED technology, depending on the market demand for performance and function.In addition to the transmit/receive branches, the amplitude-phase multifunctional chip generally also contains a common branch with digitally controlled phase shifting and attenuation functions, as well as a digital control circuit, and is generally implemented using GaAsE/D (Enhanced/De-pleted) pHEMT process.The GaNE/D process has also been initially developed, but there are no commercial products yet.

In 2010, the 55th Institute developed a GaAs K-band transceiver integrated multifunction chip fabricated using a 0.18 μm GaAsspHEMT power process. The chip integrates a power amplifier, a low-noise amplifier, and a transceiver switch. A literature report also describes a K-band transceiver multifunction GaAs MMIC chip fabricated using a 0.15 μm GaAs pHEMT power process. The receive branch achieves a gain greater than 23 dB from 19.6 to 23.0 GHz, a gain flatness of ±0.2 dB, and a noise figure below 3.5 dB. The transmit branch achieves a gain greater than 25.6 dB from 21 to 23 GHz, a saturated output power of 23.3 dBm, and an efficiency of 25.2%. The multifunction chip's transmit and receive functions are controlled by a single-pole, double-throw switch.

In 2015, Peng Longxin et al. developed a high-performance millimeter-wave transceiver multifunctional chip using a 0.15μm GaAsp HEMT power process (see Figure 1). Due to the high frequency and high power, the transmit/receive switch was externally connected.

Figure 1 Photo of the transceiver multifunction chip (size: 3.67 mm × 3.13 mm)

The receiving branch low noise amplifier adopts a three-stage amplifier topology. The total noise figure (NF) after the three-stage cascade is:

inThe following are the minimum noise figure, equivalent noise resistance, source admittance, and optimal source admittance of the tube, respectively. At a 5 V operating voltage, within the 32-37 GHz frequency band, the linear gain is (23.5 ± 1) dB, the noise figure is less than 2.5 dB, and the output power 1 dB compression point (P1dB) is greater than 6 dBm. All three stages of the low-noise amplifier utilize a self-biased source structure, as shown in Figure 2. The first-stage pHEMT utilizes optimal noise source impedance matching. It's worth noting that achieving optimal noise matching across the entire bandwidth for broadband low-noise amplifiers is impossible, which is one of the main reasons for their relatively high noise figures. On a typical Smith chart, the optimal impedance of a pHEMT rotates counterclockwise in the upper half of the chart as frequency increases, while passive components generally rotate clockwise.

Figure 2. Topology of the low-noise amplifier circuit in the receiving branch

In order to achieve optimal noise and input standing wave matching, a suitable inductor is connected in series at the source end of the pHEMT.

The transmitting branch power amplifier utilizes a three-stage amplification topology. Within the 32-36 GHz frequency band, at a voltage of 6V, it achieves a linear gain of (23 ± 0.75) dB, a saturated output power of 30 dBm, and a power-added efficiency of approximately 30%. The transmitting branch power amplifier is composed of two single-ended amplifiers (see Figure 3) combined using a Lange coupler. The output power is primarily determined by the total gate width of the final stage, which is 1.92 mm (eight cells), with a single cell size of 4 x 60 μm. To achieve high power-added efficiency, the gate width ratio of each stage is a crucial consideration. A high gate width ratio is recommended at lower frequencies, while a smaller one is recommended at higher frequencies. The pHEMT gain should also be considered, ensuring that the previous stage has sufficient power to drive the subsequent stage. To achieve high power-added efficiency, a drive ratio of 1:2:4 was used in this paper. Eight cells were chosen for the final stage rather than four because a smaller single-finger gate width offers better high-frequency characteristics, resulting in higher gain and power-added efficiency at high frequencies.

Figure 3 Single-ended power amplifier topology

The output power and efficiency of a power amplifier are primarily determined by the final output matching circuit. Accurately determining the load impedance of the final die at maximum output power and efficiency is crucial to the success of a power amplifier design. There are two general methods for determining the optimal die load impedance:

(1) According to Cripps theory, the IV characteristic curve of the die is measured to obtain the optimal resistance from the internal current source to the drain:

Where VB and DS are the source-drain breakdown voltages of the transistor, Vk is the knee voltage of the IV characteristic curve, and Imax is the source-drain current when VGS is approximately 0.7 V. The source-drain parasitic capacitance Cds and parasitic inductance Lds are then derived from the small-signal model. The load impedance of the transistor is approximately:

Where ω is the angular frequency. The optimal impedance obtained by this method has a certain deviation.

(2) Using a load-pull test system to load-pull the die, we can obtain a more accurate estimate of the die's optimal impedance, Zopt. We design a matching circuit to match four conjugated Zopt* paths in parallel to 50 Ω. Figure 4 shows the simulated impedance of a single transistor using ADS for circuit matching.

Figure 4. Simulation results of output impedance matching for a single 4×60 μm tube.

The broadband optimal impedance generally obtained by load-pull has twists and turns on the Smith chart, which can be simulated using formula (2) to obtain a smooth curve. Similarly, it is impossible for a broadband power amplifier with reactance matching to achieve optimal power matching or efficiency matching of the load impedance across the entire frequency band. This is why the power or efficiency of broadband power amplifiers is relatively low. Generally, the optimal load impedance of pHEMT/HEMT rotates counterclockwise on the Smith chart as the frequency increases, while passive components generally rotate clockwise. This phenomenon is called reverse impedance rotation, and there is no good broadband solution to this problem to date. When the bandwidth is very wide and reactance matching is difficult, other topologies with low power efficiency are generally used, such as traveling wave amplifier circuits. The main consideration for the chip's final and pre-stage matching is that, in addition to deducting losses and a certain amount of mismatch, sufficient driving power must be provided to the final stage. Otherwise, the final stage power cannot be fully output, or power pits will appear at certain frequency points. The pre-stage and input matching mainly optimize the amplifier's gain, gain flatness, and stability, while also ensuring sufficient power to drive its subsequent stages.

In 2016, Jeffery Curtis and others at Samsung developed a GaAs transceiver chip for 5G mobile communications, operating between 27.50 and 28.35 GHz. Because the chip is intended for communications systems, its design focused on efficiency at 7dB back-off in the transmit channel and DC power consumption in the receive channel. The chip's transmit channel output power at 1dB compression is 24dBm, and its power-added efficiency (PAE) reaches 14.5% at 7dB back-off. The receive channel achieves a 3.0dB noise figure with a power consumption of 35mW.

In 2018, Han Qin et al. developed a transceiver chip based on GaAsp HEMT operating at 23-25 GHz. They used current multiplexing in the circuit design to reduce power consumption. The measured receive channel gain was 23 dB, the noise figure was 2.5 dB, and the DC current was 12 mA. The transmit channel achieved saturated output power of 80 mW, a 1 dB compression point PAE of 30%, and a dynamic current of 70 mA.

In 2020, Wang Meilan and others developed a millimeter-wave transceiver chip based on an enhanced-mode GaAsp HEMT with a gate length of 0.15 μm. The switches in the transceiver chip employ a symmetrical structure with positive voltage control. In the 24.25–27.50 GHz frequency band, the transmit channel achieved a saturated output power exceeding 22 dBm and a power envelope efficiency exceeding 28%. The receive channel noise figure was below 3.0 dB, the linear gain was greater than 13 dB, and the chip achieved inter-channel isolation exceeding 20 dB.

In 2021, Mao Chenxi and others developed a Ka-band transceiver chip based on WIN Semiconductors' 0.15μmGaAsP HEMT (PP15) power process, as shown in Figure 5. A temperature-compensated attenuator was designed in the receive channel to reduce gain fluctuations at high and low temperatures. The measured receive channel noise figure was less than 3.7 dB, the gain was 28 dB, and the gain variation was 4.5 dB at high and low temperatures. The transmit channel gain was 30 dB, the saturated output power was 27.3 dBm, and the PAE was 22% at saturation.

Figure 5 Photo of Ka-band transceiver chip

In addition to integrating digitally controlled phase shifters and attenuators, amplitude and phase multi-function devices generally also integrate amplifiers, switches, and digital control circuits.

Any circuit connected in series or parallel with a transmission line introduces phase shift. Four common digital phase shifter circuits exist: switch-selectable linear, switch-selectable high- and low-pass network, loaded linear, and reflective. The basic principle of a switch-selectable linear phase shifter is shown in Figure 6. If delay lines are used in both paths I and II, the phase shift, ΔΦ, is calculated as:

Where β is the phase constant, λ is the guided wavelength, and Δl is the electrical length difference.

Figure 6 Schematic diagram of a switch-selected linear phase shifter

The switch-selectable high-pass and low-pass filter-type phase shifter is primarily based on the fact that the high-pass network transmits signals with a phase lead, while the low-pass network transmits signals with a phase lag. The circuit schematic is shown in Figure 7 and primarily includes two phase-shifting networks: a π-type and a T-type. As frequency increases, the phase lag of the low-pass network increases, while the phase lead of the high-pass network decreases. The phases of the signals passing through these two networks compensate for each other, maintaining a constant phase shift within a relatively wide bandwidth.

Figure 8 shows the schematic circuit diagram of a loaded line phase shifter. Two identical switchable loads, Y = Gi + jBi (i = 1, 2, representing the two states of the control switch), are connected in parallel at both ends of a transmission line with a characteristic impedance of Z and an electrical length of 0 (approximately λ/4). Changes in the load state cause changes in the network phase shift, thus achieving the desired phase shift. The phase shift ΔΦ₂ of the loaded line phase shifter is:

Where BN is the loaded capacitive reactance. Loaded linear phase shifters are generally used for small phase shift designs.

Figure 7. Schematic diagram of a switch-selectable high-pass and low-pass network phase shifter: (a) π-type; (b) T-type.

Figure 8 Schematic diagram of the loaded linear phase shifter circuit

The schematic diagram of a reflective digital phase shifter is shown in Figure 9. This circuit consists of a 3 dB coupler and two sets of symmetrical, switchable reflective loads. By varying the reflective loads, different insertion phase shifts can be achieved, thereby achieving phase shifting. B+ and B- represent the normalized susceptance in the two states, respectively. Reflective phase shifters are generally used for large phase shift designs.

Figure 9: Reflective digital phase shifter circuit principle

There are many different structures for phase shifters, including other types. For example, the six-phase shifter in Liu Shisheng's Ku-band multifunctional MMIC (Figure 10) consists of a cascade of 5.625°, 11.25°, 22.5°, 45°, 90°, and 180° phase shifters, creating 64 phase shift states between 0° and 360° in steps of 5.625°.

Figure 10 Schematic diagram of the 6-bit digitally controlled phase shifter structure

Because the relative phase shift of 180° is large, a structure combining a two-stage "T"-type high-pass network and a "π"-type low-pass network is adopted to expand the bandwidth. As shown in Figure 11, the single-pole double-throw switch uses GaAsMESFET as the control device, and adopts series and parallel tubes. The phase shift unit in the circuit is realized by a high-pass/low-pass network of lumped elements.

Figure 11. Schematic diagram of a 180° phase shifter

The 5.625° phase shifter utilizes a capacitor-parallel switching device as the core circuit for phase shifting, with microstrips acting as equivalent inductors at the input and output for optimal matching. The 11.25° and 22.5° phase shifters utilize an all-pass network (as shown in Figure 12), resulting in good standing wave performance and relatively low transmission loss. The 45° and 90° phase shifters combine a 5.625° phase shifter network structure with an all-pass network structure, achieving high phase shift and relatively good impedance matching while simultaneously compensating for transmission loss and the slope of the additional amplitude modulation. Typically, the 180° and 90° phase shifters are placed on either side of the phase shifter circuit, while smaller phase shifters are sandwiched in between to protect their accuracy and minimize the pull of external impedance at the input/output ports.

Figure 12 Circuit diagram of 22.5° and 11.25° phase shifters

Common digital attenuator topologies include switch selectionAttenuators include the T-type attenuator (see Figure 13), the T-type attenuator (see Figure 14), the π-type attenuator (see Figure 15), the reflective attenuator (see Figure 16), the capacitor-compensated T-type attenuator (see Figure 17), the inductor-compensated π-type attenuator (see Figure 18), and the small-bit attenuator (see Figure 19). To achieve attenuators with wider bandwidths, lower additive phase shift, and better input-output matching, attenuator structures are improved for different attenuation levels. Typical improved attenuator structures include simplified T-type attenuation networks, capacitor-compensated T-type attenuation networks, and inductor-compensated π-type attenuation networks.

Figure 13 Schematic diagram of a switch-selectable attenuator

Figure 14 (a) T-type attenuator; (b) simplified T-type attenuator

Figure 15 Schematic diagram of a π-type attenuator

Figure 16 Schematic diagram of a reflective attenuator

Figure 17 Schematic diagram of capacitor-compensated T-type attenuation

Figure 18 Inductance compensation π-type attenuation diagram

Figure 19: Schematic diagram of a small attenuator

There are other types of attenuator circuit structures, such as the 6-bit digitally controlled attenuator in Liu Shisheng's Ku-band multifunctional MMIC (see Figure 20). When C is high, the attenuator is in the reference state; when C is high, the attenuator is in the attenuation state.

Figure 20 6-bit digitally controlled attenuator structure

The 16 dB attenuator uses a standard single-pole, double-throw switch as the digitally controlled attenuation network for the channel selector switch. The reference path is a microstrip delay path, and the attenuation path is a π-type attenuation impedance network. The microstrip delay path compensates for phase shift caused by parasitic elements and signal transmission length (matching microstrip and resistors) in the π-type attenuation impedance network. This ensures equal phase shift in both paths, resulting in a low additive phase shift. Both input and output channels use appropriate microstrip lines to achieve impedance matching to the channel selector switch based on switch design principles, effectively reducing input and output standing wave ratios.

The 8dB attenuator utilizes a modified "T"-type attenuation impedance network. Because the standard "T"-type attenuation impedance network has a relatively small parallel resistance, which has the greatest impact on attenuation accuracy, to account for process variations, the parallel resistance is treated as three parallel resistors. This reduces the impact of process variations and improves design accuracy. Input and output matching is also based on the principle of switch matching. The 1dB, 2dB, and 4dB attenuators utilize a standard "T"-type attenuation network. The reference path utilizes a series switch device to achieve low reference-state transmission loss.

The 0.5 dB attenuator can be realized by using a simplified "T" type attenuation network because the small series resistance in the "T" type attenuation network is easily affected by the process and has little effect on the input and output standing waves.

Under existing material and process technology conditions, digital control circuits for GaAs and GaN multifunctional circuits are generally implemented using GaAsE/D and GaNE/D processes. Depending on the specific needs of digital circuits, the basic logic units of GaAs FET digital circuits take various forms, primarily including buffered FET logic (BFL), Schottky diode FET logic (SDFL), direct-coupled FET logic (DCFL), and source-coupled FET logic (SCFL). For details, please refer to the literature.

In 2006, M/A-COM announced the launch of a commercial dual-channel X-band 7~12GHz multi-function MMIC MAM-FGM0001-DIE (see Figure 21), which includes a 6-phase shifter, a 6-bit attenuator (LSB is 0.5 dB), a gain block, an excitation amplifier, and a switch. It measures 6.000mmX4.000mmx0.075mm, has a receive channel gain of 21dB, a transmit channel gain of 28dB, an output P1B of 22dBm, and also integrates a 24-bit serial port.

Figure 21 X-band MAMFGM0001-DIE: (a) structural diagram; (b) photograph

The XZ1002-BD chip, launched by M/A-com in 2008, consists of a single-pole double-throw (SPDT) switch, an LNA, a 6-bit digital phase shifter, a driver amplifier, and a 5-bit digital attenuator, with a TTL parallel data input, as shown in Figure 22. It operates from 8.5 to 11 GHz, offers a receive gain of 21 dB and an output third-order intermodulation (OIP3) of 28 dBm; a transmit gain of 19 dB and a Pu of 23.5 dBm. The chip measures 5.0 mm x 4.0 mm x 0.1 mm.

Figure 22 XZ1002-BD multi-function MMIC:(a) Schematic diagram;(b) Chip photo

The CHC3014 chip, launched by UMS in February 2009, is shown in Figure 23. It operates at 8 to 12 GHz and uses a 0.25 μm GaAs E/D HEMT process. The 6-bit phase shifter has a minimum phase shift of 5.625°, a maximum phase shift of 360°, and a root mean square error (RMS) of 2°. The 6-bit attenuator has a minimum bit of 0.55 dB, a maximum bit of 34.6 dB, and an RMS of 0.3 dB. The 2-bit adjustable attenuator has an MSB of 6 dB in 2 dB steps. The receive branch gain is 13.5 dB, the noise figure (NF) is 5.8 dB, and the power factor is 16.5 dBm. The transmit branch gain is 25 dB, and the saturated power factor (P) is 20 dBm. The DA and SPDT interfaces are TTL-compatible parallel interfaces with a control level of 0/3.3 V.

Figure 23. Schematic diagram of the UMS 8-12 GHz CHC3014 multi-function MMIC chip.

In 2018, Jin Cheol Jeong, In Bok-Yom, and others released a multifunctional delay chip for active phased array systems (see Figure 24). Operating at 6 to 18 GHz, it integrates 8-bit delay, 7-bit attenuation, and serial-to-parallel conversion functions in a 4mm x 5mm footprint. By utilizing a delay element, this chip achieves excellent broadband performance. Measured delay RMS error (RMS) is less than 1.7 ps, delay parasitic amplitude modulation is less than 2.1 dB, attenuation RMS error is less than 0.9 dB, attenuation additive phase shift is less than 5°, small signal gain is 12 dB, and output power is 16.5 dBm.

Figure 24 Micrograph of the time-delay multifunctional chip

In 2019, Jin Cheol Jeong, Manseok, and others released a multifunctional chip for phased array applications in satellite and 5G communications (see Figure 25). Operating at frequencies from 20 to 32 GHz, the chip integrates six-bit phase shift, six-bit attenuation, and serial-to-parallel conversion functions in a 3 mm x 3 mm footprint. Test results show that the chip achieves a small-signal gain of 2 dB, a phase shift RMS error of less than 5°, and an attenuation RMS error of less than 0.3 dB.

Figure 25 Micrograph of a multifunctional chip used for satellite and 5G communications

That same year, Shancheng Zhou et al. released a dual-channel, high-precision amplitude-phase multifunction chip for satellite communication phased arrays (see Figure 26). Operating at 7.5 to 9.0 GHz, the chip integrates six phase shifts, six attenuations, and serial-to-parallel conversion functions, measuring 3.5 mm x 4.5 mm. Measured insertion loss was less than 13 dB, attenuation RMS error was less than 0.45 dB, and phase shift RMS error was less than 2°.

Figure 26 Dual-channel high-precision amplitude and phase multifunctional chip

In 2020, Hyunkyu Lee, Younghwan Kim, and others released a Ku-band multifunctional chip with switchable transmit and receive modes (see Figure 27). Operating at 12 to 18 GHz, the chip integrates 4-bit phase shift, 5-bit attenuation, and serial-to-parallel conversion, with a chip area of 11.7 mm². The chip utilizes a broadband, high-gain power amplifier with a peak gain of 27.3 dB to improve overall channel gain. This power amplifier achieves an output 1dB compression point of 18.9 dBm and consumes 380 mW. A low-noise amplifier with a noise figure as low as 0.74 dB was also designed to reduce channel noise. The measured transmit channel gain was 16.5 dB, the output power 1dB compression point was 19.2 dBm, the attenuation RMS error was less than 0.6 dB, and the phase RMS error was less than 6.4°. The receive channel gain was 17.3 dB, the noise figure was 4.3 dB, the attenuation RMS error was less than 0.7 dB, and the phase RMS error was less than 5.1°.

Figure 27 Ku-band multifunctional chip with switchable transmit and receive states

That same year, Zhou Shouli, Zhang Jingle, and others released a W-band amplitude-phase multifunction chip (see Figure 28). Operating at 96–105 GHz, the chip integrates 6-bit phase shift, 6-bit attenuation, and 2-bit delay functions, measuring 5.0 mm x 3.5 mm. This chip incorporates a 2-bit delay within its amplitude-phase multifunction architecture, effectively reducing the spatial dispersion of the beam and increasing the scanning angle and instantaneous bandwidth of the phased array system. Test results show that the chip exhibits transmit gain greater than 7 dB and receive gain greater than 3 dB; transmit 1 dB compression points greater than 7.5 dBm and receive 1 dB compression points greater than 5 dBm; attenuation root mean square error less than 0.4 dB, and phase shift root mean square error less than 3.5°.

Figure 28. Amplitude and phase multifunctional chip for W band

In 2021, Ding Youyuan, Wang Qingsong, and others released an LS-band broadband multifunction chip (see Figure 29). Operating at 0.5 to 2.7 GHz, the chip integrates a parallel driver, phase shifters, and a power divider, measuring 3.4 mm x 1.8 mm. The chip's phase shifters utilize a magnetically coupled all-pass network (MCAPN) structure, while the power divider is integrated using lumped elements. This not only reduces the chip area but also achieves excellent phase accuracy and amplitude consistency over an ultra-wideband range. Measured insertion loss is less than 7 dB, phase error is less than 8°, and parasitic amplitude modulation is less than 0.8 dB.

Figure 29 LS band broadband multifunctional chip

In 2023, Yang Yuan, Jialong Zeng, and others released a high-precision, multi-function X-band amplitude and phase control chip with switchable transmit and receive modes (see Figure 30). Operating at 8 to 11 GHz, the chip integrates 6-bit phase shift, 6-bit attenuation, and serial-to-parallel conversion functions. The chip measures 4.30 mm x 2.85 mm. Test results show that the chip's attenuation root mean square error is less than 0.28 dB, and its phase shift root mean square error is less than 3.3°. The chip also boasts a receive gain of 8.9 dB and an output 1dB compression point of 7.8 dBm. The chip also boasts a transmit gain of 15.9 dB and an output 1dB compression point of 11.9 dBm.

Figure 30: X-band high-precision amplitude and phase multi-function chip with switchable transmit and receive states

That same year, Chiara Ramella et al. released a multifunctional amplitude-phase chip for active electronically scanned arrays (see Figure 31). Operating at 7.6 to 9.1 GHz, the chip integrates six-bit phase shift, six-bit attenuation, and serial-to-parallel conversion functions, measuring 6 mm². Using ultra-low-power digital logic circuits, the chip consumes 43 mW overall, with an average of 2.2 mW per control bit. Test results show an insertion loss of 16 dB.

Figure 31 Micrograph of digital circuit part

In a T/R assembly, the low-noise amplifier (LNA) is closely connected to the antenna, potentially subjecting it to high input power and potentially damaging it. Therefore, a limiter is required for protection. For decades, the LNA and limiter were separate chips, cascaded together, increasing chip size and assembly complexity. Recent advances in materials processing have enabled the epitaxial growth of pHEMT materials on GaAs substrates, followed by the epitaxial growth of PIN transistor materials, integrating the limiter and LNA on the same substrate. This effectively reduces chip size, saves costs, and eases chip assembly complexity, leading to the development of a low-noise integrated limiter design.

The design of a limiting low-noise amplifier generally begins by independently designing the limiter and low-noise amplifier, then combining them for optimization. It's important to independently observe the stability of the amplifier to ensure its stability. References to the literature are available for limiter design. Based on high-power requirements, the I layer thickness and surface structure of the GaAs PIN diode are optimized, and the surface dimensions are then determined. Large and small signal models are then established. Through optimized design, while the limiter can withstand 100W of input power, low insertion loss is also achieved. To achieve a lower noise figure for the limiting low-noise amplifier, a new design approach uses the entire limiter as an input match for the low-noise amplifier, significantly reducing the overall noise figure.

Figure 32. Photo of a 7-13 GHz high-power limiting low-noise amplifier monolithic chip.

In 2018, the 13th Institute developed a Ka-band GaAs MMIC limiting low-noise amplifier (Figure 33). Its noise figure is less than 3.1dB, its linear gain is greater than 18dB, and its quiescent operating current is 20mA. At a constant temperature of 70°C, it can withstand a pulse power of 2W (pulse width 4ms, duty cycle 30%).

Figure 33 Photo of a 5-6 GHz limiting low-noise amplifier chip

In 2019, the 55th Institute developed a millimeter-wave GaAs monolithic limiting low-noise amplifier (see Figure 34). The limiter utilizes a two-stage anti-parallel diode structure. By optimizing the limiter matching circuit, the limiter's power handling capability was increased and the insertion loss of the limiting circuit was reduced. The low-noise amplifier features a four-stage cascade design, employing minimum noise matching at the input. An RC series resonant circuit is added to the bias circuit to reduce noise and improve circuit stability. Measured within the 33-37 GHz frequency band, the gain reaches (22 ± 1) dB, the noise figure is less than 3.0 dB, the output P1aB exceeds 5 dBm, and it can withstand a pulsed input power of 15 W.

Figure 34: Millimeter-wave GaAs limiting low-noise amplifier chip

In 2020, the 55th Institute developed a 5-6 GHz limiting low-noise amplifier. This amplifier utilizes parallel negative feedback, source-stage inductor negative feedback, and a current-reuse structure to reduce power consumption while improving gain flatness and stability. Within the operating frequency band, the amplifier achieves a gain of (27 ± 0.2) dB, a noise figure of 1.1-1.3 dB, a total power consumption of 240 mW, and a power handling capability exceeding 46 dBm (2 ms pulse width, 30% duty cycle). The chip measures 3.3 mm x 1.3 mm.

In 2021, Zeng Zhi et al. developed a 5-13 GHz GaAs limiting low-noise amplifier (MMIC) (see Figure 35). The limiter utilizes a three-stage antiparallel diode structure, and the LNA employs two-stage negative feedback and source inductor matching, achieving flat gain and low noise in the 5-13 GHz range. The small-signal gain is greater than 20 dB, the noise figure is less than 1.8 dB, the power handling capability is greater than 46 dBm (pulse width 2 ms, duty cycle 30%), and the total power consumption is less than 190 mW.

Figure 35: Photo of the 5-13 GHz GaAs limiting LNA integrated chip

In 2022, Di Yuehong et al. developed a 32-40 GHz high-power PIN diode-limited low-noise amplifier (Figure 36). To reduce the amplifier's noise figure, they proposed a "T"-type matching unit consisting of an inductor and a PIN diode. Multiple matching units were cascaded to form the input matching network of the low-noise amplifier. The chip was fabricated using a PIN/0.15 μm HEMT integrated process. Measurements showed that the chip could withstand continuous waves up to 38 dBm for 30 minutes without damage. Within the 32-40 GHz frequency range, the circuit's small-signal gain and noise figure were (18 ± 0.4) dB and 2.5-2.8 dB, respectively.

Figure 36: 32-40 GHz PIN-limited low-noise amplifier MMIC

Although the transceiver chip made with GaAspHEMT process still has certain advantages in terms of power consumption and noise in the receiving channel, due to the characteristics of the material itself, the saturated output power of the transmitting branch of the GaAspHEMT transceiver chip is mostly below 1W.If higher transmission power is required, the total output gate width of the power amplifier needs to be increased, which increases the chip area. In addition, the output switch cannot withstand higher power (generally, it can only withstand a maximum of about 1W).The power performance is far from meeting the requirements of electronic warfare systems for transceiver chips.

GaN HEMT transceiver chips offer significant advantages in terms of high power and efficiency in the transmit channel. Their output switches can handle over 10W of power, overcoming the low power handling capacity of GaAs/HEMT switches. However, a drawback is that the low-noise amplifier in the receive channel requires a relatively high voltage (≥8V) to operate, resulting in high power consumption. New GaN processes are currently being developed to address this issue.

In 2012, Masuda S. et al. from Fujitsu Laboratories in Japan presented the first GaN transceiver MMIC at the MTT-S. This chip, which integrates a power amplifier (PA), LNA, and SPDT switch, operates in the X-band and is fabricated using a 0.25μm-gate-length SiC-based GaN HEMT process. The PA subcircuit in this transceiver chip achieves a saturated output power of 42.8dBm at 10.5 GHz and a power envelope efficiency (PAE) of 52%. However, the SPDT switch in the chip exhibits a small-signal insertion loss of 1.2 dB and a PA of only 39.2dBm. Limited by the insertion loss and power handling of the SPDT switch, the overall transceiver chip achieves a saturated output power of only 38.2 dBm at this frequency.

E. Limiti's team at the University of Rome II in Italy has made significant contributions to GaN transceiver chips. In 2015, Limiti et al. designed a C-band transceiver MMIC based on a 0.25μm UMS GaN process and a 0.50μm SLX GaN process. The paper presented only simulation results for both chips: within the 5.2-5.6GHz operating band, the transmit channel saturated output power exceeded 40W, with a power gain greater than 36dB. The PAEs for the two process designs were 38% and 27%, respectively, and the receive channel noise figure was below 2.5dB. In 2017, A. Salvucci of the same team designed a transceiver chip operating in the same frequency band based on a Leonardo foundry 0.25μm GaN process. Similarly, they presented only simulation results: receive noise was below 2dB, transmit power reached 44W, and PAE reached 42%.

In 2016, Biondi et al. from the MEC Lab reported at EuMIC a transceiver chip based on a 0.25μm GaN process. The chip operates between 8.6 and 11.2 GHz and includes a PA, LNA, and antenna-side switch. The chip's switch introduces an absorptive load to the PA in receive mode. This ensures proper loading of the PA during receive, avoiding unstable behavior and potential malfunctions that could occur if the PA remains powered on during a delay between the PA shutdown and Rx enable commands. Test results show that the chip achieves a saturated output power of 39dBm in the transmit channel with a PAE of 25%. The receive channel consumes 800mW and has a noise figure between 2 and 3dB.

Reports of fully monolithic T/R chips with integrated transmit and receive amplitude and phase are rare worldwide. In 2016, Nanjing Institute of Technology (Nanjing 55 Research Institute) reported on a GaN Ku-band GaNT/R transceiver amplitude and phase multifunction MMIC, which was published in a paper in 2017 (Figure 37). This chip integrates the T/R receive, transmit, and common channels. The receive channel includes a power output switch, a pre-stage low-noise amplifier, a 5-bit digital attenuator, a post-stage low-noise amplifier, and a small-signal switch. The transmit channel includes a 5-bit digital phase shifter, a small-signal switch, a driver amplifier, a power amplifier, and a power switch. The common channel also includes a 5-bit digital phase shifter, as shown in Figure 37. Measured within the 16-17 GHz operating frequency range, the receive channel gain was ≥ (20 ± 0.5) dB, the noise figure was ≤ 3.5 dB, the transmit channel gain was approximately 21 dB, the saturated power was approximately 41 dBm (pulse width 100 μs, duty cycle 10%), and the power-added efficiency was approximately 30%, as shown in Figures 38-40. The integrated phase shifting and attenuation functions on the chip functioned normally.

Figure 37. Ku-band GaN T/R integrated multifunctional transceiver monolithic chip: (a) circuit schematic; (b) photo

Figure 38 Gain and noise figure test results of the receiving branch

Figure 39 Transmitter branch output power, power gain, and efficiency test results

Figure 40 (a) 32-bit attenuation state and (b) 32-bit phase shift state test results

The bias voltage of the receive branch low-noise amplifier circuit is 10V, and the total quiescent current is 140mA. Compared to GaAs, the operating voltage and current are significantly higher. Reducing the voltage decreases the receive gain, as shown in Figure 41, and the noise also increases significantly. This is due to the material and process characteristics of GaN HEMT. To address the issue of high power consumption in the receive branch, the 55th Institute developed a new process in terms of materials and processes, aiming to maintain the power advantage while reducing power consumption in the receive branch.

Figure 41: Receive gain decreases as voltage decreases

In 2022, Kong Lingzheng developed a Ku-band transceiver multifunction chip using a dual-gate-length GaN integrated process (see Figure 42). This chip integrates a low-noise amplifier (LNA) for the receive channel and a power amplifier (PA) for the transmit channel, using a single-pole, double-throw (SPDT) switch for switching between channels. The chip utilizes two GaN HEMT processes with different gate lengths. The LNA utilizes a 0.10μm low-voltage, low-noise process, while the PA and switch utilize a 0.15μm high-voltage, high-power process. These two transistors are integrated on the same SiC substrate. Test results show that within the 14-18 GHz band, the transmit channel achieves a linear gain of ≥30 dB, a saturated output power of ≥40.5 dBm, and a typical power-added efficiency of 23%. The receive channel achieves a linear gain of (24 ± 0.2) dB, a typical noise figure of 2.3 dB, and power consumption of only 140 mW (5V/28 mA). The chip measures 4.0 mm x 3.0 mm.

Figure 42 Photo of the transceiver multifunctional chip

For low-noise devices, a high-barrier Ni gate structure is used to reduce gate leakage current and improve device noise performance. By reducing the source-drain spacing, the device's on-state resistance and knee voltage are reduced, allowing the low-noise transistor to operate in the saturation region at a drain voltage of 2V, thus realizing a current-reuse structure, as shown in Figure 43.

Figure 43 GaN LNA circuit topology

The PA circuit utilizes a three-stage amplification structure. Generally, the optimal power impedance curve and the optimal efficiency impedance curve measured using load-pull measurements within the operating bandwidth do not coincide. To meet power and efficiency requirements, a compromise is necessary. Figure 44 shows the impedance matching of a 6x75μm die in the final-stage unit cell. Within the 14-18 GHz operating frequency band, the designed matching curve (blue) lies between the optimal efficiency impedance curve (black) and the optimal power impedance curve (red). Figure 45 shows the overall circuit topology of the GaNPA. To improve circuit stability, small parallel resistors are used between adjacent cells in the final stage to suppress odd-mode oscillations and reduce signal crosstalk between adjacent cells.

Figure 44 PA final stage matching impedance

Figure 45 GaN PA circuit topology

In 2018, Rocco Giofrè and others from the Limiti team reported at T-MTT a transceiver MMIC operating in the S-band with a relative bandwidth of 13%. The chip was fabricated using the UMS 0.25μm GaN process. To achieve single-supply control and targeted optimization of both switch arms, an asymmetric switch design was employed. Both the low-noise amplifier and the power amplifier employed a three-stage reactance matching structure. Test results showed that the chip's transmit channel achieved a saturated output power exceeding 40W, a linear gain ≥35dB, and a power envelope of 42%. The receive channel achieved a noise figure below 1.75dB and a linear gain greater than 30dB at a power consumption of 1350mW. The chip measures 7.0mm x 7.0mm.

In 2019, Giofrè et al. reported at MWCL on an improved version of the aforementioned S-band transceiver chip, further improving power and efficiency. In the transmit channel, by introducing a Class F harmonic termination, they achieved a saturated output power of nearly 47dBm and a power envelope efficiency exceeding 48%. In the receive channel, they reduced DC power consumption from 1350mW to 900mW without compromising noise and gain performance.

In 2020, Giofre et al. extended this work to the C-band using a similar circuit topology. They developed a transceiver chip operating in the 5.25–5.57 GHz band based on a 0.25 μm GaN process. The chip's switches utilize parallel resonance technology, reducing insertion loss within the band. The chip's transmit channel also achieves a saturated output power of 40 W with a PAE of 30%, while the receive channel achieves a 3.2 dB noise figure at a low power consumption of 250 mW.

In 2020, Lorenzo Pace and others applied the OMMICD01GH process, further extending the operating frequency to higher frequencies and developing a Ka-band transceiver chip. The back-end chip-side switch, which has minimal impact on chip performance, uses a series and parallel structure for its two branches to facilitate single-power supply control. The antenna-side switch uses a parallel structure and introduces parallel inductor resonance to achieve lower insertion loss. The chip operates in the 35.0-36.5 GHz frequency band, with a saturated output power ≥32 dBm, a PAE ≥24%, and a noise figure of 3.5 dB.

In 2022, LonghiPE et al. developed a Ka-band transceiver chip (see Figure 46) based on two GaN HEMT integration processes with different gate lengths. The chip was integrated using OMMIC's 100nm D01GH and 60nm D006GH processes. 60nm gate length die were used for the power amplifier and low-noise amplifier input stages to improve transmit channel efficiency and receive channel noise, while 100nm gate length die were used for the remaining transistors to ensure chip power performance. Furthermore, unlike the 50Ω system impedance of the chip's external ports, the impedance of the chip's cascade ports connecting the switch, PA, and LNA is 40Ω to minimize insertion loss due to cascade matching. The chip's transmit channel achieves 35dBm saturated output power and 18% PAE, while the receive channel has a noise figure of 3.2dB and consumes 200mW.

Figure 46 Ka-band GaN transceiver chip:(a) Structural diagram;(b) Photographs

In 2017, Weijun Luo et al. published a GaNE/D5 digitally controlled phase shifter. This E/D digital circuit converts the TTL (0-5V) control voltage into two complementary negative voltages (0-5V and -5-0V), thus reducing the number of control terminals by half. However, no GaNE/D integrated products have yet been commercially released.

author:Peng Longxin Zou Wenjing Kong Lingzheng Zhang Zhanlong

Source: Research and Progress in Solid-State Electronics

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